From: Jan Kneschke <Jan.Kneschke@kiel.netsurf.de>
  To  : ggi-develop@eskimo.com
  Date: Tue, 8 Sep 1998 23:35:55 +0200 (MEST)

programming of clocks

i stumbled over a piece of documention and wonder why i read the following:

VGA-Hardware (s3-vision):
	MISC-register
		bit3-2
		00 = select 25.175 MHz as DCLK
		01 = select 28.322 MHz as DLCK
		11 = enhanced clocks 
Clock-Chip (tvp3026)
	PLLSEL
		00 = select 25.175 MHz as DCLK
		01 = select 28.322 MHz as DLCK
		11 = set by Pixel Clock PLL

i think this two bit are harwired to the PLLSEL-facility of the clock-chip.
is this true ?? if no, how to change the PLLSEL-lines ?

the clock-chip offers the possiblity to ignore the PLLSEL-line, but this
facility isn't used here.

i just read that MISC-bits using the 8bit-data-path to the clock-chip. 
so, who set the PLLSEL-lines ???


thats all
  Jan

--- 
       Project: GGI - S3-Vision-driver -- http://www.ggi-project.org/
         -)=  Jan (Weigon) Kneschke -- Kiel -- Northern Germany =(-