From: Martin Lexa <mlexa@atlas.cz>
  To  : ggi-develop@eskimo.com
  Date: Sat, 07 Aug 1999 10:22:19 +0200

S3 ViRGE FIFO

Hi all!

  I'm sending here patch for 70%-solving the noising
problem.
  Please try all options it has and send me your
results which one is best for you. We need results
from all types of ViRGE cards (VX, DX/GX, GX2, ...) to
choose best option which will go to ViRGE driver.
So this patch is only for testing and will probably not
go to cvs tree.
  On my S3 ViRGE (rev. 6) 86C325 I get non-noising
8, 15, 16)bit depth up to 1024x768 resolution.
24bit depth is a problem, with FIFO_TYPE set to 3 you
will probably get only non-noising 640x480. When change
to 32bit depth nothing will help you. If you want
32bit depth you have to decrease vertical refresh rate
of your monitor.

Bye, Martin
		[E-mail: mlexa@atlas.cz]
diff -u --recursive --new-file kgicon.orig/kgi/chipset/S3/virge.c kgicon/kgi/chipset/S3/virge.c
--- kgicon.orig/kgi/chipset/S3/virge.c	Sat Jul 31 10:18:44 1999
+++ kgicon/kgi/chipset/S3/virge.c	Fri Aug  6 20:46:35 1999
@@ -45,6 +45,23 @@
 #define ViRGE
 #define	HARDWARE_TEXT_CURSOR	0
 
+/* 
+   0 - use standard values
+   
+   1 - low FIFO treshold    - the best performance (like XFree FIFO
+       aggressive option)
+       
+   2 - medium FIFO treshold - medium performance (like XFree FIFO
+       moderate option)
+       
+   3 - high FIFO treshold   - the worst performance (like XFree FIFO
+       conservative option with some higher values in 24/32 depth)
+       
+   Use above values to get better performance (the second value) or to reduce
+   pixel noising effect in higher resolutions and depths (the fourth value).
+*/
+#define FIFO_TYPE 0
+
 #include "S3/virge.h"
 
 #define	IO_VGA_BASE	0x03C0
@@ -213,7 +230,20 @@
   s3_ViRGE_default_interrupt
 };
 
-/* Waring: do not compile this "inline" ! Pointer to procedure needed */
+/* Memory controller registers */
+struct virge_memcntl_struct
+{
+  kgiu32 offset;
+  kgiu32 data;
+} virge_memcntl[] = 
+{
+  { 0x0200, 0x00010400 } , /*  0 FIFO Control    */
+  { 0x0204, 0x00000000 } , /*  1 MIU Control     */
+  { 0x0208, 0x00000808 } , /*  2 Streams Timeout */
+  { 0x020C, 0x08080810 }   /*  3 Misc Timeout    */
+};
+
+/* Warning: do not compile this "inline" ! Pointer to procedure needed */
 void s3_ViRGE_default_interrupt (struct kgi_display *dpy) {
   return;
 }
@@ -1306,11 +1336,65 @@
 	setup.SEQ[0x01] |= SR01_DISPLAY_OFF; 
 	SEQ_out8(dpy, setup.SEQ[0x01], 0x01);
 
+	/* Default values for memory controller registers */
+	virge_memcntl[0].data = 0x10400;
+	virge_memcntl[1].data = 0x0;   
+	virge_memcntl[2].data = 0x808;  
+	virge_memcntl[3].data = 0x8080810; 
+	
+	/* Prepare memory controller registers */
+	if (FIFO_TYPE > 0) {
+	  virge_memcntl[1].data = 0x200;
+	  virge_memcntl[2].data = 0x1808;
+	  virge_memcntl[3].data = 0x8081810;
+	}
+
 	/* Prepare subsystems */
 	kgim_monitor_set_mode(dpy, mode);
 	NOTICE2("monitor set");
 	kgim_ramdac_set_mode(dpy, mode);
 	NOTICE2("ramdac set");
+	
+	/* Adjusting FIFO slots */
+	switch(mode->request.graphtype) {
+	    case KGIGT_8BIT:
+	    case KGIGT_15BIT:
+	    case KGIGT_16BIT:
+	      if (FIFO_TYPE == 1) virge_memcntl[0].data -= 0xc000;
+	      else if (FIFO_TYPE == 2) virge_memcntl[0].data -= 0x8000;
+	      break;
+	    case KGIGT_24BIT:
+	      if (cardtype == vx || cardtype == gx2 || cardtype == mx)
+	        virge_memcntl[0].data = 0xc098;
+	      else if (cardtype == virge || cardtype == dxgx)
+	        virge_memcntl[0].data = 0xc000;
+	      if (FIFO_TYPE == 1) virge_memcntl[0].data -= 0x6000;
+	      else if (FIFO_TYPE == 2) virge_memcntl[0].data -= 0x4000;
+	  /* Delete line below if you get some errors when FIFO_TYPE is 3 */
+	      else if (FIFO_TYPE == 3) virge_memcntl[0].data = 0x10400;
+	      break;
+	    case KGIGT_32BIT:
+	      if (cardtype == vx) virge_memcntl[0].data = 0xc098;
+	      else if (cardtype == virge || cardtype == dxgx)
+	        virge_memcntl[0].data = 0x10000; 
+	      if (FIFO_TYPE == 1) virge_memcntl[0].data -= 0x6000;
+	      else if (FIFO_TYPE == 2) virge_memcntl[0].data -= 0x4000;
+	  /* Delete line below if you get some errors when FIFO_TYPE is 3 */
+	      else if (FIFO_TYPE == 3) virge_memcntl[0].data = 0x10400;
+	      break;
+	    default:
+	      break;
+	}
+
+	for (foo = 100000; foo > 0; foo--) 
+    	  if (mem_in8(MEM_VGA + 0x03DA) & 0x08) break;
+	if (foo == 0) DEBUG1("ViRGE: VSYNC not found.");	
+	
+	for (foo = 0; foo < 4; foo++)
+	  SPR_out32(dpy, virge_memcntl[foo].offset, virge_memcntl[foo].data);	
+	DEBUG1("ViRGE: FIFO slot: 0x%x", virge_memcntl[0].data);
+	
+	/* Prepare subsystems */
 	kgim_clock_set_mode(dpy, mode);
 	NOTICE2("clock set");
 	restore_state(dpy, &setup);
diff -u --recursive --new-file kgicon.orig/kgi/ramdac/S3/virge.c kgicon/kgi/ramdac/S3/virge.c
--- kgicon.orig/kgi/ramdac/S3/virge.c	Wed Aug  4 22:27:44 1999
+++ kgicon/kgi/ramdac/S3/virge.c	Fri Aug  6 20:26:18 1999
@@ -104,7 +104,6 @@
   { 0x01F4, 0x027F01E0 } , /* 19 Primary stream window size (width,height) */
   { 0x01F8, 0x00000000 } , /* 20 Secondary stream window base */
   { 0x01FC, 0x00020001 } , /* 21 Secondary stream window size */
-  { 0x0200, 0x00006000 } , /* 22 FIFO Control */
 }; 
 
 #define	CTRL0		private->ctrl0
@@ -175,12 +174,10 @@
     case KGIGT_24BIT:
       virge_streams[0].data = 0x06000000;
       virge_streams[8].data = 3*(mode->request.virt.x);
-      virge_streams[22].data= 0xc000;
       break;
     case KGIGT_32BIT:
       virge_streams[0].data = 0x07000000;
       virge_streams[8].data = 4*(mode->request.virt.x);
-      virge_streams[22].data= 0x10000;
       break;
     default:
       DEBUG1("Wrong colour depth for Streams.");
@@ -205,7 +202,7 @@
     virge_streams[15].data = 0; /* Vertical output equals frame size. */
   }
   ENTER_CRITICAL; 
-  for (i=0;i<23;i++)
+  for (i=0;i<22;i++)
     SPR_out32(dpy,virge_streams[i].offset,virge_streams[i].data);
   LEAVE_CRITICAL;
 }