From: Andreas Beck <becka@rz.uni-duesseldorf.de>
  To  : ggi-develop@eskimo.com
  Date: Fri, 6 Aug 1999 01:39:06 +0200

Re: Matrox GGI accellerator

> > >         line_y 0x35
> > >         line_y_mask 0xff13;
> > Again this requires very fine grain control over hardware access. Is
> It is impossible on any MMU I have ever heard of. 

Yes. You need SW assistance for it. That is catching the trap, analyzing it
and the deciding. Asking the kernel right away is faster.

> 	I would actually say that under no circumstances should it be
> _necessary_ to give userspace direct access to hardware registers in order to
> get acceptable performance or implement a direct rendering model.  A command
> FIFO with ping-pong buffers will reduce the number of kernel-user transitions
> to a level where they are no longer the weak link in the performance chain. 
> Latency will go up somewhat, but given that most video hardware cannot
> display more than ~100 frames per second anyway, this is unlikely to be a
> noticeable problem.

I second that. If a card is nicely designed, fine. If not, we can fall back
to a "streaming" feed to the accelerator and be happy.

Reading on, I see, that I can do nothing but agree :-).

CU, Andy

-- 
= Andreas Beck                    |  Email :  <andreas.beck@ggi-project.org> =