From: Peter Hawkins <dph-man@iname.com>
  To  : ggi-develop@eskimo.com
  Date: Tue, 11 Aug 1998 21:31:24 +1000

Patch for Mach64.h (minor)

Hi there...
Ok, here's a patch for Mach64 support. Since we nicked (within the terms
of the license it's ok) kgicon/kgi/include/ATI/Mach64.h from Xfree86
anyway, we might as well have the latest version of it.

Diff is attached. Ok ok, it doesn't do much at all, but I'm at least
working on it a bit...
:-)
Peter

2c2
<  * Copyright 1992,1993,1994,1995,1996 by Kevin E. Martin, Chapel Hill, North Carolina.
---
>  * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina.
26,27c26,27
<  * 
<  * Modified for Linux-GGI use by Jason McMullan (jmcc@cs.cmu.edu)
---
>  *
>  * Modified (not much) for Linux-GGI by Peter Hawkins (dph-man@iname.com)
30,31c30,45
< #ifndef _Mach64_H_
< #define _Mach64_H_
---
> #ifndef _MACH64_H
> #define _MACH64_H
> 
> /* NON-GUI IO MAPPED Registers */
> 
> extern unsigned ioCONFIG_CHIP_ID;
> extern unsigned ioCONFIG_CNTL;
> extern unsigned ioSCRATCH_REG0;
> extern unsigned ioSCRATCH_REG1;
> extern unsigned ioCONFIG_STAT0;
> extern unsigned ioMEM_CNTL;
> extern unsigned ioDAC_REGS;
> extern unsigned ioDAC_CNTL;
> extern unsigned ioGEN_TEST_CNTL;
> extern unsigned ioCLOCK_CNTL;
> extern unsigned ioCRTC_GEN_CNTL;
57a72,76
> #define DSP_CONFIG              0x0020  /* Dword offset 08 */
> #define DSP_ON_OFF              0x0024  /* Dword offset 09 */
> 
> #define SHARED_CNTL             0x0038  /* Dword offset 0E */
> 
67a87,88
> #define HW_DEBUG                0x007C  /* Dword offset 1F */
> 
175d195
< #define NUM_CTL_REGS		0x0400
201a222
> #define CRTC_LOCK_REGS		0x00400000
249a271,275
> /* HW_DEBUG register constants */
> /* For RagePro only... */
> #define AUTO_FF_DIS             0x000001000
> #define AUTO_BLKWRT_DIS         0x000002000
> 
252a279
> #define BUS_APER_REG_DIS        0x00000010
259a287,298
> /* DSP_CONFIG register constants */
> #define DSP_XCLKS_PER_QW        0x00003fff
> #define DSP_LOOP_LATENCY        0x000f0000
> #define DSP_PRECISION           0x00700000
> 
> /* DSP_ON_OFF register constants */
> #define DSP_OFF                 0x000007ff
> #define DSP_ON                  0x07ff0000
> 
> /* SHARED_CNTL register constants */
> #define CTD_FIFO5               0x01000000
> 
330,333c369,373
< #define DRAM			0
< #define EDO_DRAM		1
< #define PSEUDO_EDO		2
< #define SDRAM			3
---
> #define DRAM			1
> #define EDO_DRAM		2
> #define PSEUDO_EDO		3
> #define SDRAM			4
> #define SGRAM			5
372a413
> #define MEM_SIZE_16M		0x00000006
377a419
> #define MEM_SIZE_16M_GTB	0x0000000F
387,392c429,441
< #define PCI_MACH64_GX		0x4758
< #define PCI_MACH64_CX		0x4358
< #define PCI_MACH64_CT		0x4354
< #define PCI_MACH64_ET		0x4554
< #define PCI_MACH64_VT		0x5654
< #define PCI_MACH64_GT		0x4754
---
> #define PCI_MACH64_GX_ID	0x4758
> #define PCI_MACH64_CX_ID	0x4358
> #define PCI_MACH64_CT_ID	0x4354
> #define PCI_MACH64_ET_ID	0x4554
> #define PCI_MACH64_VT_ID	0x5654
> #define PCI_MACH64_VU_ID	0x5655
> #define PCI_MACH64_GT_ID	0x4754
> #define PCI_MACH64_GU_ID	0x4755
> #define PCI_MACH64_GB_ID	0x4742
> #define PCI_MACH64_GD_ID	0x4744
> #define PCI_MACH64_GI_ID	0x4749
> #define PCI_MACH64_GP_ID	0x4750
> #define PCI_MACH64_GQ_ID	0x4751
407a457
> #define MACH64_VU_ID		0x5655
409,417c459,465
< 
< /* Mach64 chip types */
< #define MACH64_UNKNOWN		0
< #define MACH64_GX		1
< #define MACH64_CX		2
< #define MACH64_CT		3
< #define MACH64_ET		4
< #define MACH64_VT		5
< #define MACH64_GT		6
---
> #define MACH64_GU_ID		0x4755
> #define MACH64_GB_ID		0x4742
> #define MACH64_GD_ID		0x4744
> #define MACH64_GI_ID		0x4749
> #define MACH64_GP_ID		0x4750
> #define MACH64_GQ_ID		0x4751
> #define MACH64_UNKNOWN_ID	0x0000
623,625c671,672
< #define WaitQueue(v,func,args...) \
< 	{ while ((REGr(FIFO_STAT) & 0xffff) > \
< 	  ((unsigned short)(0x8000 >> (v)))) func(args); }
---
> #define WaitQueue(v)    { while ((regr(FIFO_STAT) & 0xffff) > \
> 			 ((unsigned short)(0x8000 >> (v)))); }
628,630c675,676
< #define WaitIdleEmpty(func,args...) \
< 	{ WaitQueue(16,func,##args); \
< 	  while ((REGr(GUI_STAT) & 1) != 0) func(args); }
---
> #define WaitIdleEmpty() { WaitQueue(16); \
> 			  while ((regr(GUI_STAT) & 1) != 0); }
636,641c682,687
<     WaitQueue(5,schedule); \
<     REGw(SRC_Y_X, (((_srcx) << 16) | ((_srcy) & 0x0000ffff))); \
<     REGw(SRC_WIDTH1, (_w)); \
<     REGw(DST_CNTL, (_dir)); \
<     REGw(DST_Y_X, (((_dstx) << 16) | ((_dsty) & 0x0000ffff))); \
<     REGw(DST_HEIGHT_WIDTH, (((_w) << 16) | ((_h) & 0x0000ffff))); \
---
>     WaitQueue(5); \
>     regw(SRC_Y_X, (((_srcx) << 16) | ((_srcy) & 0x0000ffff))); \
>     regw(SRC_WIDTH1, (_w)); \
>     regw(DST_CNTL, (_dir)); \
>     regw(DST_Y_X, (((_dstx) << 16) | ((_dsty) & 0x0000ffff))); \
>     regw(DST_HEIGHT_WIDTH, (((_w) << 16) | ((_h) & 0x0000ffff))); \
644c690,694
< #endif /* _Mach64_H_ */
---
> #ifndef NULL
> #define NULL    0
> #endif
> 
> #endif /* REGMACH64_H */