From: Stefan Mars <mars@lysator.liu.se>
  To  : ggi-develop@eskimo.com
  Date: Tue, 1 Sep 1998 10:44:19 +0200 (MET DST)

ViRGE clock driver.

Morning everyone,

I am working on a much better clockdriver for the ViRGE (and I suppose,
TRIO) integrated clocks, and I have already caught a few errors/problems
in the old one.

However, not having done a clockdriver before I do have some questions.

Calculating the dclk is no problem at all, and I even have a way of doing
it without division, which is a bad thing in the kernel. However, I don't
see a good way of deciding about the MCLK, is that completly up to me?

The fields in the mode structure seems to be more related to LCLK than to
DCLK. Would someone please explain their relationship?

-Stefan

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